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general description the MAX5182 is a dual, 10-bit, alternate-phase-update, current-output digital-to-analog converter (dac) designed for superior performance in systems requiring analog signal reconstruction with low distortion and low-power operation. the max5185 provides equal specifications with on-chip output resistors for voltage- output operation. both devices are designed for 10pv-s glitch operation, to reduce distortion and minimize unwanted spurious signal components at the output. an on-board +1.2v bandgap circuit provides a well-regu- lated, low-noise reference that can be disabled for external reference operation. the MAX5182/max5185 are designed to provide a high level of signal integrity for the least amount of power dis- sipation. both dacs operate from a +2.7v to +3.3v sin- gle supply. additionally, these dacs have three modes of operation: normal, low-power standby, and complete shutdown. a full shutdown provides the lowest possible power dissipation with a maximum shutdown current of 1?. fast wake-up time (0.5?) from standby mode to full dac operation allows for power conservation by activating the dacs only when required. the MAX5182/max5185 are available in a 28-pin qsop package and are specified for the extended (-40? to +85?) temperature range. for pin-compatible 8-bit versions, refer to the max5188/max5191 data sheet. applications signal reconstruction digital signal processing arbitrary waveform generators (awgs) imaging applications features +2.7v to +3.3v single-supply operation wide spurious-free dynamic range: 70db at f out = 2.2mhz fully-differential outputs for each dac 0.5% fsr gain mismatch between dac outputs low-current standby or full-shutdown modes internal +1.2v low-noise bandgap reference small 28-pin qsop package MAX5182/max5185 dual, 10-bit, 40mhz current/voltage alternate-phase output dacs ________________________________________________________________ maxim integrated products 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 cref2 out2p out2n refo refr dgnd d3 dv dd d9 d8 d7 d6 d5 d4 d2 d1 d0 ren n.c. clk cs pd dacen av dd agnd out1n out1p cref1 qsop top view MAX5182 max5185 19-1578; rev 3; 12/01 part MAX5182 beei -40? to +85? temp. range pin-package 28 qsop pin configuration ordering information max5185 beei -40? to +85? 28 qsop for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
lsb 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av dd = dv dd = +3v ?0%, agnd = dgnd = 0, f clk = 40mhz, i fs = 1ma, 400 ? differential output, c l = 5pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd , dv dd to agnd, dgnd .................................-0.3v to +6v digital inputs to dgnd.............................................-0.3v to +6v out1p, out1n, out2p, out2n, cref1, cref2 to agnd ...................................................-0.3v to +6v v ref to agnd ..........................................................-0.3v to +6v agnd to dgnd.....................................................-0.3v to +0.3v av dd to dv dd .................................................................... ?.3v maximum current into any pin............................................50ma continuous power dissipation (t a = +70?) 28-pin qsop (derate 9.00mw/? above +70?)....... 725mw operating temperature ranges max518_beei................................................-40? to +85? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) ................................ +300? MAX5182/max5185 db f clk = 40mhz full-scale output current i fs 0.5 1 1.5 ma dac external output resistor load r l 400 ? MAX5182 only MAX5182 only parameter symbol min typ max units full-scale error -40 ?5 +40 lsb -2 +2 differential nonlinearity dnl -1 ?.5 +1 lsb output settling time 25 ns glitch impulse 10 pvs spurious-free dynamic range to nyquist sfdr 72 dbc 57 70 resolution n 10 bits integral nonlinearity inl -2 ?.5 +2 lsb total harmonic distortion to nyquist thd -70 db -68 -63 signal-to-noise ratio to nyquist snr 61 db 56 59 dac-to-dac ouput isolation -60 db clock and data feedthrough 50 nvs output noise 10 pa/ hz gain mismatch between dac outputs ?.5 ? % fsr full-scale output voltage v fs 400 mv voltage compliance of output -0.3 0.8 v output leakage current -1 1 ? conditions f clk = 40mhz (note 1) MAX5182 guaranteed monotonic to ?.5lsb error band f clk = 40mhz f out = 2.2mhz all 0s to all 1s f out = 2.2mhz, t a = +25? dacen = 0, MAX5182 only -8 +8 max5185 zero-scale error static performance dynamic performance analog output dual, 10-bit, 40mhz current/voltage alternate-phase output dacs f out = 550khz f out = 2.2mhz, t a = +25? f out = 550khz f out = 2.2mhz, t a = +25? f out = 550khz f out = 2.2mhz, t a = +25?
MAX5182/max5185 dual, 10-bit, 40mhz current/voltage alternate-phase output dacs _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = dv dd = +3v ?0%, agnd = dgnd = 0, f clk = 40mhz, i fs = 1ma, 400 ? differential output, c l = 5pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) note 1: excludes reference and reference resistor (max5185) tolerance. cs fall to clk rise time 5 ns cs fall to clk fall time 5 ns dacen rise time to v out_ 0.5 ? pd fall time to v out_ 50 ? clock period t clk 25 ns clock high time t ch 10 0 ns clock low time t cl 10 ns digital input voltage high v ih 2 v digital input voltage low v il 0.8 v digital input current i in ? ? digital input capacitance c in 10 pf dac1 data to clk rise setup time t ds1 10 ns dac2 data to clk fall setup time t ds2 10 ns dac1 clk rise to data hold time t dh1 0 ns dac2 clk fall to data hold time t dh2 0 ns v in = 0 or dv dd output voltage temperature drift tcv ref 50 ppm/? reference output drive capability i refout 10 ? reference supply rejection 0.5 mv/v current gain (i fs / i ref ) 8 ma/ma analog power-supply voltage av dd 2.7 3.3 v analog supply current i avdd 2.7 5.0 ma digital power-supply voltage dv dd 2.7 3.3 v digital supply current i dvdd 4.2 5.0 ma standby current i standby 1.0 1.5 ma shutdown current i shdn 0.5 1 ? pd = 0, dacen = 1, digital inputs at 0 or dv dd pd = 0, dacen = 1, digital inputs at 0 or dv dd pd = 0, dacen = 0, digital inputs at 0 or dv dd pd = 1, dacen = x, digital inputs at 0 or dv dd (x = don? care) parameter symbol min typ max units conditions output voltage range v ref 2.7 1.2 1.28 v reference power requirements logic inputs and outputs timing characteristics
MAX5182/max5185 dual, 10-bit, 40mhz current/voltage alternate-phase output dacs 4 _______________________________________________________________________________________ typical operating characteristics (av dd = dv dd = +3v, agnd = dgnd = 0, 400 ? differential output, i fs = 1ma, c l = 5pf, t a = +25?, unless otherwise noted.) 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 0 128 256 384 512 640 768 896 1024 integral nonlinearity vs. input code MAX5182/85-01 input code inl (lsb) 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0 128 256 384 512 640 768 896 1024 differential nonlinearity vs. input code MAX5182/85-02 input code dnl (lsb) 3.00 2.75 2.50 2.25 2.00 2.5 4.0 3.0 3.5 4.5 5.0 5.5 analog supply current vs. supply voltage MAX5182/85-03 supply voltage (v) analog supply current (ma) MAX5182 max5185 3.00 2.75 2.25 2.50 2.00 -40 35 -15 10 60 85 analog supply current vs. temperature MAX5182/85-04 temperature (?) analog supply current (ma) MAX5182 max5185 10 8 6 4 2 0 2.5 4.0 3.0 3.5 4.5 5.0 5.5 digital supply current vs. supply voltage MAX5182/85-05 supply voltage (v) digital supply current (ma) MAX5182 max5185 4.00 3.75 3.25 3.50 3.00 -40 35 -15 10 60 85 digital supply current vs. temperature MAX5182/85-06 temperature ( c) digital supply current (ma) MAX5182 max5185 620 610 600 580 590 570 560 2.5 4.0 3.0 3.5 4.5 5.0 5.5 standby current vs. supply voltage MAX5182/85-07 supply voltage (v) standby current ( a) MAX5182 max5185 600 590 570 560 580 550 -40 35 -15 10 60 85 MAX5182/max5185 standby current vs. temperature MAX5182/85-08 temperature ( c) standby current (ma) MAX5182 max5185 0.8 0.7 0.6 0.5 0.4 2.5 4.0 3.0 3.5 4.5 5.0 5.5 shutdown current vs. supply voltage MAX5182/85-09 supply voltage (v) shutdown current ( a) MAX5182 max5185
MAX5182/max5185 dual, 10-bit, 40mhz current/voltage alternate-phase output dacs _______________________________________________________________________________________ 5 1.28 1.27 1.26 1.25 1.24 1.23 2.5 4.0 3.0 3.5 4.5 5.0 5.5 internal reference voltage vs. supply voltage MAX5182/85-11 supply voltage (v) reference voltage (v) MAX5182 max5185 1.28 1.27 1.25 1.24 1.26 1.23 -40 35 -15 10 60 85 internal reference voltage vs. temperature MAX5182/85-12 temperature ( c) reference voltage (v) MAX5182 max5185 4 3 1 2 0 0 125 250 375 500 output current vs. reference current MAX5182/85-13 reference current ( a) output current (ma) dynamic response rise time MAX5182/85-14 50ns/div out_p 150mv/ div out_n 150mv/ div dynamic response fall time MAX5182/85-15 50ns/div out_p 150mv/ div out_n 150mv/ div settling time MAX5182/85-16 12.5ns/div out_n 100mv/ div out_p 100mv/ div 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0246 8101214 16 18 20 fft plot, dac1 max5181/4toc17 output frequency (mhz) (dbc) f out = 2.2mhz f clk = 40mhz 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0246 8101214 16 18 20 MAX5182/85-18 output frequency (mhz) (dbc) fft plot, dac2 f out = 2.2mhz f clk = 40mhz 40 70 60 50 80 90 100 10 30 25 15 20 35 40 45 50 55 60 MAX5182/85-19 clock frequency ( mhz ) sfdr (dbc) spurious-free dynamic range vs. clock frequency dac2 dac1 typical operating characteristics (continued) (av dd = dv dd = +3v, agnd = dgnd = 0, 400 ? differential output, i fs = 1ma, c l = 5pf, t a = +25?, unless otherwise noted.)
MAX5182/max5185 dual, 10-bit, 40mhz current/voltage alternate-phase output dacs 6 _______________________________________________________________________________________ 66 68 72 70 76 74 78 500 1100 1300 700 900 1500 1700 1900 2100 2300 MAX5182/85-20 output frequency (khz) sfdr (dbc) spurious-free dynamic range vs. output frequency and clock frequency, dac1 f clk = 50mhz f clk = 40mhz f clk = 60mhz f clk = 20mhz f clk = 10mhz f clk = 30mhz 66 72 70 68 74 76 78 500 1100 1300 700 900 1500 1700 1900 2100 2300 MAX5182/85-21 output frequency (khz) sfdr (dbc) spurious-free dynamic range vs. output frequency and clock frequency, dac2 f clk = 30mhz f clk = 60mhz f clk = 10mhz f clk = 50mhz f clk = 40mhz f clk = 20mhz 62.5 62.0 61.0 60.5 61.5 60.0 0 1500 500 1000 2000 2500 signal-to-noise plus distortion vs. output frequency MAX5182/85-23 output frequency (khz) sinad (db) dac2 dac1 -140 -100 -120 -60 -80 -20 0 -40 20 06 4 210 814 12 18 16 20 MAX5182/85-25 output frequency (mhz) sfdr (dbc) multitone spurious-free dynamic range vs. output frequency 60 62 64 66 68 70 72 74 0.50 0.75 1.00 1.25 1.50 spurious-free dynamic range vs. full-scale output current MAX5182/85-26 full-scale output current (ma) sfdr (dbc) typical operating characteristics (continued) (av dd = dv dd = +3v, agnd = dgnd = 0, 400 ? differential output, i fs = 1ma, c l = 5pf, t a = +25?, unless otherwise noted.)
MAX5182/max5185 dual, 10-bit, 40mhz current/voltage alternate-phase output dacs _______________________________________________________________________________________ 7 clock input clk 9 no connection. do not connect to this pin . n.c. 10 active-low reference enable. connect to dgnd to activate the on-chip +1.2v reference. ren 11 data bit d0 (lsb) to data bit d9 (msb) d0?9 12?1 digital supply, +2.7v to +3.3v dv dd 22 analog positive supply, +2.7v to +3.3v av dd 5 dac enable, digital input 0: enter dac standby mode with pd = dgnd 1: power-up dac with pd = dgnd x: enter shutdown mode with pd = dv dd (x = don? care) dacen 6 power-down select 0: enter dac standby mode (dacen = dgnd) or power-up dac (dacen = dv dd ) 1: enter shutdown mode pd 7 active-low chip select cs 8 analog ground agnd 4 negative analog output, dac1. current output for MAX5182; voltage output for max5185. out1n 3 pin positive analog output, dac1. current output for MAX5182; voltage output for max5185. out1p 2 reference bias bypass, dac1 cref1 1 function name positive analog output, dac2. current output for MAX5182; voltage output for max5185. out2p 27 reference bias bypass, dac2 cref2 28 negative analog output, dac2. current output for MAX5182; voltage output for max5185. out2n 26 reference output refo 25 reference input refr 24 digital ground dgnd 23 ______________________________________________________________pin description
MAX5182/max5185 dual, 10-bit, 40mhz current/voltage alternate-phase output dacs 8 _______________________________________________________________________________________ detailed description the MAX5182/max5185 are dual, 10-bit digital-to-ana- log converters (dacs) capable of operating with clock speeds up to 40mhz. each of these dual converters consists of separate input and dac registers, followed by a current-source array capable of generating up to 1.5ma full-scale output current (figure 1). an integrated +1.2v voltage reference and control amplifier determine the data converters?full-scale output currents/voltages. careful reference design ensures close gain matching and excellent drift characteristics. the max5185, with its voltage output operation, features matched 400 ? on- chip resistors that convert the current from the current array into a voltage. internal reference and control amplifier the MAX5182/max5185 provide an integrated 50ppm/?, +1.2v, low-noise bandgap reference, which can be disabled and overridden by an external refer- ence voltage. refo serves either as an input for an external reference or as an output for the integrated ref- erence. if ren is connected to dgnd, the internal ref- erence is selected and refo provides a +1.2v output. due to its limited 10? output drive capability, the refo pin must be buffered with an external amplifier if heavier loading is required. the MAX5182/max5185 also employ a control amplifier designed to simultaneously regulate the full-scale out- put current ifs for both outputs of the ics. the output current is calculated as follows: i fs = 8 ? i ref where i ref is the reference output current (i ref = v refo /r set ), and i fs is the full-scale output current. r set is the reference resistor that determines the amplifier? output current (figure 2) on the MAX5182. this current is mirrored into the current-source array, where it is equally distributed between matched current segments, and summed to valid output current read- ings for the dacs. inside the max5185, each output current (dac1 and dac2) is converted to an output voltage (v out1 , v out2 ) with two internal, ground-referenced 400 ? load resistors. using the internal +1.2v reference voltage, the max5185? integrated reference output current resistor (r set = 9.6k ? ), sets i ref to 125? and i fs to 1ma. 9.6k * refr refo 1.2v ref ren current- source array dac 1 switches dac 2 switches 400 ? msb decode clk output latches output latches msb decode *internal 400 ? and 9.6k ? resistors for max5185 only. av dd agnd cs dacen pd * * * * dv dd dgnd cref2 MAX5182 max5185 cref1 out2p out1p out2n out1n 400 ? d9 d0 400 ? 400 ? input latches input latches figure 1. functional diagram
MAX5182/max5185 dual, 10-bit, 40mhz current/voltage alternate-phase output dacs _______________________________________________________________________________________ 9 9.6k i fs 0.1 f 10 f dv dd r set i ref refr agnd agnd dgnd av dd * refo +1.2v bandgap reference ren current- source array external +1.2v reference *9.6k ? reference current-set resistor internal to max5185 only. use external r set for MAX5182. MAX5182 max5185 max6520 figure 3. MAX5182/max5185 with external reference r set 9.6k i fs r set c comp * refr agnd dgnd agnd i ref ** refo max4040 +1.2v bandgap reference ren current- source array *compensation capacitor (comp 100nf) **9.6k ? reference current-set resistor internal to max5185 only. use external r set for MAX5182. optional external buffer for heavier loads MAX5182 max5185 i ref = v ref r set figure 2. setting i fs with the internal +1.2v reference and the control amplifier
MAX5182/max5185 dual, 10-bit, 40mhz current/voltage alternate-phase output dacs 10 ______________________________________________________________________________________ pd (power-down select) dacen (dac enable) power-down mode output state 0 0 standby MAX5182 high-z max5185 agnd 0 1 wake-up last state prior to standby mode 1 x shutdown MAX5182 high-z max5185 agnd table 1. power-down mode selection x = don? care external reference to disable the MAX5182/max5185? internal reference, connect ren to dv dd . a temperature-stable, external reference may now be applied to drive the refo pin (figure 3) to set the full-scale output. be sure to choose a reference capable of supplying at least 150? to drive the bias circuit that generates the cascode cur- rent for the current array. for improved accuracy and drift performance, chose a fixed output voltage refer- ence such as the +1.2v, 25ppm/? max6520 bandgap reference. standby mode to enter the lower power standby mode, connect digital inputs pd and dacen to dgnd. in standby, both the reference and the control amplifier are active, with the current array inactive. to exit this condition, dacen must be pulled high with pd held at dgnd. the MAX5182/max5185 typically require 50? to wake up and let both outputs and reference settle. shutdown mode for lowest power consumption, the MAX5182/max5185 provide a power-down mode in which the reference, control amplifier, and current array are inactive and the dacs supply current is reduced to 1?. to enter this mode, connect pd to dv dd . to return to active mode, connect pd to dgnd and dacen to dv dd . about 50? are required for the devices to leave the shutdown mode and to settle their outputs to the values prior to shutdown. table 1 lists the power-down mode selection. timing information both internal dac cells write to their outputs in alternate phase (figure 4). the input latch of the first dac (dac1) is loaded after the clock signal transitions high. when the clock signal transitions low, the input latch of the second dac (dac2) is loaded. the contents of the first input latch are shifted into the dac1 register on the rising edge of the clock; the contents of the second input latch are shifted into the input register of dac2 on the falling edge of the clock. both outputs are updated on alternate phases of the clock. clk d0 d9 out1 n - 2 dac1 dac2 dac1 dac2 dac1 dac2 n - 1 n - 1 n - 1 n n n n + 1 n + 1 t ds1 t ch t cl t clk out2 n - 1 n - 2 n t ds1 t dh1 t dh2 figure 4. timing diagram
MAX5182/max5185 dual, 10-bit, 40mhz current/voltage alternate-phase output dacs ______________________________________________________________________________________ 11 outputs the MAX5182 outputs are designed to supply 1ma full- scale output currents into 400 ? loads in parallel with a 5pf capacitive load. the max5185 features integrated 400 ? resistors that restore the array currents into pro- portional, differential voltages of 400mv. these differ- ential output voltages can then be used to drive a balun transformer or a low-distortion, high-speed operational amplifier to convert the differential voltage into a single- ended voltage. applications information static and dynamic performance definitions integral nonlinearity integral nonlinearity (inl) (figure 5a) is the deviation of the values on an actual transfer function from either a best-straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. for a dac, the deviations are mea- sured every single step. differential nonlinearity differential nonlinearity (dnl) (figure 5b) is the differ- ence between an actual step height and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes and a monotonic transfer function. offset error offset error (figure 5c) is the difference between the ideal and the actual offset point. for a dac, the offset point is the step value when the digital input is zero. this error affects all codes by the same amount and can usually be compensated by trimming. figure 5a. integral nonlinearity figure 5b. differential nonlinearity figure 5c. offset error figure 5d. gain error 0 2 1 4 3 7 6 5 000 010 001 011 100 101 110 at step 011 (1/2 lsb ) at step 001 (1/4 lsb ) 111 digital input code analog output value 0 2 1 4 3 6 5 000 010 001 011 100 101 differential linearity error (-1/4 lsb) differential linearity error (+1/4 lsb) 1 lsb 1 lsb digital input code analog output value 0 2 1 3 000 010 001 011 actual diagram ideal diagram actual offset point offset error (+1 1/4 lsb) ideal offset point digital input code analog output value 0 5 4 6 7 000 101 100 110 111 ideal diagram gain error (-1 1/4 lsb) ideal full-scale output actual full-scale output digital input code analog output value
MAX5182/max5185 dual, 10-bit, 40mhz current/voltage alternate-phase output dacs 12 ______________________________________________________________________________________ gain error gain error (figure 5d) is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corre- sponds to the same percentage error in each step. settling time settling time is the amount of time required from the start of a transition until the dac output settles its new output value to within the converter? specified accuracy. digital feedthrough digital feedthrough is the noise generated on a dac? output when any digital input transitions. proper board layout and grounding will significantly reduce this noise, but there will always be some feedthrough caused by the dac itself. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the input signal? first four harmonics to the fun- damental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next-largest distortion component. differential to single-ended conversion the max4108 low-distortion, high-input bandwidth amplifier may be used to generate a voltage from the MAX5182? current array output. the differential voltage across out1p (or out2p) and out1n (or out2n) is converted into a single-ended voltage by designing an appropriate operational amplifier configuration as shown in figure 6. grounding and power-supply decoupling grounding and power-supply decoupling strongly influ- ence the performance of the MAX5182/max5185. unwanted digital crosstalk may couple through the input, reference, power-supply, and ground connec- tions, which may affect dynamic specifications like sig- nal-to-noise ratio or sfdr. in addition, electromagnetic interference (emi) can either couple into or be generat- ed by the MAX5182/max5185. therefore, grounding and power-supply decoupling guidelines for high- speed, high-frequency applications should be closely followed. first, a multilayer pc board with separate ground and power-supply planes is recommended. high-speed signals should run on controlled impedance lines directly above the ground plane. since the MAX5182/ max5185 have separate analog and digital ground buses (agnd and dgnd, respectively), the pc board should also have separate analog and digital ground sections with only one point connecting the two. digital signals should run above the digital ground, and plane and analog signals should run above the analog ground plane. both devices have two power-supply inputs: analog v dd (av dd ) and digital v dd (dv dd ). each av dd input should be decoupled with parallel 10? and 0.1? ceramic chip capacitors as close to the pin as possi- ble. their opposite ends should have the shortest pos- sible connection to the ground plane. the dv dd pins should also have separate 10? and 0.1? capacitors, again adjacent to their respective pins. try to minimize the analog load capacitance for proper operation. for best performance, it is recommended to bypass cref1 and cref2 with low-esr 0.1? capacitors to av dd . the power-supply voltages should also be decoupled at the point they enter the pc board with large tantalum or electrolytic capacitors. ferrite beads with additional decoupling capacitors forming a pi network could also improve performance. thd vvvv v = +++ ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 1 log
MAX5182/max5185 dual, 10-bit, 40mhz current/voltage alternate-phase output dacs ______________________________________________________________________________________ 13 chip information transistor count: 9464 substrate connected to agnd ren agnd dgnd out1p cref2 cref1 out1n out2p out2n 0.1 f 0.1 f 0.1 f av dd av dd av dd r set ** *400 ? resistors internal to max5185 only. **MAX5182 only. MAX5182 max5185 10 f +3v +3v 0.1 f 0.1 f clk refr refo d0 d9 10 f 400 ? * 400 ? * 402 ? 402 ? 402 ? 402 ? 402 ? 402 ? 402 ? 402 ? +5v -5v dv dd output1 400 ? * 400 ? * +5v -5v output2 max4108 max4108 figure 6. differential to single-ended conversion using a low-distortion amplifier
MAX5182/max5185 dual, 10-bit, 40mhz current/voltage alternate-phase output dacs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information qsop.eps

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